1. Field of the Invention
The present invention is related to a shift register, and more particularly, to a shift register of a liquid crystal display device.
2. Description of the Prior Art
Liquid crystal display (LCD) devices, characterized in low radiation, thin appearance and low power consumption, have gradually replaced traditional cathode ray tube display (CRT) devices and been widely used in electronic devices such as notebook computers, personal digital assistants (PDAs), flat panel TVs or mobile phones. Traditional LCD devices display image by driving the pixels of the LCD panel using external driving chips. In order to reduce the number of devices and manufacturing costs, GOA (gate on array) technique has been developed in which the gate driver is directly fabricated on the LCD panel.
Reference is made to FIG. 1 for a simplified block diagram of a prior art LCD device 100. FIG. 1 only illustrates partial structure of the LCD device 100, including a plurality of gate lines GL(1)-GL(N), a shift register 110, a clock generator 120, and a power supply 130. For operating the shift register 110, the clock generator 120 provides a start pulse signal VST and two clock signals CK and XCK, while the power supply 130 provides a bias voltage VSS. The clock signals CK and XCK periodically switch between a high voltage level and a low voltage level and have opposite polarities at the same time. The shift register 110 includes a plurality of shift register units SR(1)-SR(N) coupled in series. Each shift register unit is coupled to a corresponding gate line, a first input end IN1 of a next-stage shift register unit, and a second input end IN2 of a prior-stage shift register unit. According to the clock signals CK, XCK and the start pulse signal VST, the shift register 110 can sequentially output gate driving signals GS(1)-GS(N) to the corresponding gate lines GL(1)-GL(N) using the shift register units SR(1)-SR(N), respectively.
Reference is made to FIG. 2 for a diagram illustrating an nth-stage shift register unit SR(n) of the LCD device 100 (n is an integer between 1 and N). The shift register unit SR(n) includes an first input end IN1, a second input end IN2, an output end OUT, a node Q(n), an input circuit 10, a pull-up circuit 20, a pull-down circuit 30, and a maintain circuit 40. The first input end IN1 of the shift register unit SR(n) is coupled to the output end of the (n−1)th shift register unit SR(n−1), the second input end IN2 of the shift register unit SR(n) is coupled to the output end of the (n+1)th shift register unit SR(n+1), and the output end OUT of the shift register unit SR(n) is coupled to the first input end of the (n+1)th shift register unit SR(n+1) and the gate line GL(n). In the prior art LCD device 100, the transistor switch T1 of the input circuit 10 maintains the voltage level of the node Q(n) according to the (n−1)th-stage gate driving signal GS(n−1), the transistor switches T2 and T3 of the pull-up circuit 20 output the gate driving signal GS(n) respectively according to the voltage level of the node Q(n) and the (n+1)th-stage gate driving signal GS(n+1), the transistor switch T4 of the pull-down circuit 30 maintains the voltage level of the node Q(n) according to the (n+1)th-stage gate driving signal GS(n+1), and the transistor T5 of the maintain circuit 40 controls the signal transmission path between the node Q(n) and the output end OUT according to the clock signal CK. Since the (n+1)th-stage gate driving signal GS(n+1) is required for maintaining the voltage level of the node Q(n), the prior art LCD device 100 has complicated circuit layout and fails to stabilize the voltage level of the output end OUT effectively.
Reference is made to FIG. 3 for a simplified block diagram of a prior art LCD device 200. FIG. 2 only illustrates partial structure of the LCD device 200, including a plurality of gate lines GL(1)-GL(N), a shift register 210, a clock generator 220, and a power supply 230. For operating the shift register 210, the clock generator 220 provides a start pulse signal VST and two clock signals CK and XCK, while the power supply 230 provides bias voltages VDD and VSS. The clock signals CK and XCK periodically switch between a high voltage level and a low voltage level and have opposite polarities at the same time. The shift register 210 includes a plurality of shift register units SR(1)-SR(N) coupled in series. Each shift register unit is coupled to a corresponding gate line and a next-stage shift register unit. According to the clock signals CK, XCK and the start pulse signal VST, the shift register 210 can sequentially output gate driving signals GS(1)-GS(N) to the corresponding gate lines GL(1)-GL(N) using the shift register units SR(1)-SR(N), respectively.
Reference is made to FIG. 4 for a diagram illustrating an nth-stage shift register unit SR(n) of the LCD device 200 (n is an integer between 1 and N). The shift register unit SR(n) includes an input end IN(n), an output end OUT(n), an input circuit 10, a pull-up circuit 20, and a pull-down circuit 30. The input end IN(n) of the shift register unit SR(n) is coupled to the (n−1)th shift register unit SR(n−1), while the output end OUT(n) of the shift register unit SR(n) is coupled to the (n+1)th shift register unit SR(n+1) and the gate line GL(n). In the prior art LCD device 200, the transistor switch T1 of the input circuit 10 maintains the voltage level of the node Q(n) according to the gate driving signal GS(n−1), the transistor switches T2 and T3 of the pull-up circuit 20 output the gate driving signal GS(n) respectively according to the voltage levels of the nodes Q1(n) and Q2(n), the transistor switches T4-T6 of the pull-down circuit 30 maintain the voltage levels of the nodes Q1(n) and Q2(n). Although the (n+1)th-stage gate driving signal GS(n+1) is not required as a feedback signal, the prior art LCD device 200 still has a complicated circuit layout.